//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
//Date        : Mon Nov 11 18:52:03 2019
//Host        : DESKTOP-EVCEGS1 running 64-bit major release  (build 9200)
//Command     : generate_target Add_4bit_v3.bd
//Design      : Add_4bit_v3
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CORE_GENERATION_INFO = "Add_4bit_v3,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=Add_4bit_v3,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=5,numReposBlks=5,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=5,bdsource=USER,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "Add_4bit_v3.hwdef" *) 
module Add_4bit_v3
   (A0,
    A1,
    A2,
    APM,
    B0,
    B1,
    B2,
    BPM,
    Y0,
    Y1,
    Y2,
    Y3,
    Y4);
  input A0;
  input A1;
  input A2;
  input APM;
  input B0;
  input B1;
  input B2;
  input BPM;
  output Y0;
  output Y1;
  output Y2;
  output Y3;
  output Y4;

  wire A0_1;
  wire A1_1;
  wire A2_1;
  wire APM_1;
  wire Add_1bit_0_CO;
  wire Add_1bit_0_Y;
  wire Add_1bit_1_CO;
  wire Add_1bit_1_Y;
  wire Add_1bit_2_CO;
  wire Add_1bit_2_Y;
  wire Add_1bit_3_CO;
  wire Add_1bit_3_Y;
  wire Add_1bit_4_Y;
  wire B0_1;
  wire B1_1;
  wire B2_1;
  wire BPM_1;

  assign A0_1 = A0;
  assign A1_1 = A1;
  assign A2_1 = A2;
  assign APM_1 = APM;
  assign B0_1 = B0;
  assign B1_1 = B1;
  assign B2_1 = B2;
  assign BPM_1 = BPM;
  assign Y0 = Add_1bit_0_Y;
  assign Y1 = Add_1bit_2_Y;
  assign Y2 = Add_1bit_1_Y;
  assign Y3 = Add_1bit_3_Y;
  assign Y4 = Add_1bit_4_Y;
  Add_4bit_v3_Add_1bit_0_0 Add_1bit_0
       (.A(A0_1),
        .B(B0_1),
        .CI(1'b0),
        .CO(Add_1bit_0_CO),
        .Y(Add_1bit_0_Y));
  Add_4bit_v3_Add_1bit_0_1 Add_1bit_1
       (.A(A2_1),
        .B(B2_1),
        .CI(Add_1bit_2_CO),
        .CO(Add_1bit_1_CO),
        .Y(Add_1bit_1_Y));
  Add_4bit_v3_Add_1bit_1_0 Add_1bit_2
       (.A(A1_1),
        .B(B1_1),
        .CI(Add_1bit_0_CO),
        .CO(Add_1bit_2_CO),
        .Y(Add_1bit_2_Y));
  Add_4bit_v3_Add_1bit_1_1 Add_1bit_3
       (.A(APM_1),
        .B(BPM_1),
        .CI(Add_1bit_1_CO),
        .CO(Add_1bit_3_CO),
        .Y(Add_1bit_3_Y));
  Add_4bit_v3_Add_1bit_3_0 Add_1bit_4
       (.A(APM_1),
        .B(BPM_1),
        .CI(Add_1bit_3_CO),
        .Y(Add_1bit_4_Y));
endmodule
